The present invention relates generally to any electronic system or module which includes embedded actives and discrete passives, and methods for use in fabricating a system or module with embedded active and discrete passive devices.
Embedded actives (active devices) have been realized as a promising package technology to achieve an ultra-miniaturized form factor as well as better electrical performance by burying active chips directly into a core or build-up layers. In addition to active ICs, discrete passives such as capacitors, resistors, inductors, IPDs (integrated passive devices) and other similar discretes can be also embedded. Embedded active technology is mainly used for portable applications that require extremely small form-factors and lower power. Cell phones and laptop PCs, for example, having a 2004 world market size of 150 billion and 60 billion U.S. dollars, respectively, are the most representative items. Since the use of portable devices has expanded rapidly in recent years and its trend should continue, it is expected that the demand for embedded active becomes tremendous.
Active ICs have been embedded into a core or build-up layers in many different ways, with the following being a broad classification of the approaches involved: chip-first, chip-middle, and chip-last.
In the chip-first approach, embedding starts typically with actives and build up of wiring takes place on top of the actives. Demonstratio7n of this chip-first embedded active dates back to 1975 by Yokogawa (see U.S. Pat. No. 3,903,590). Multiple semiconductor chips are mounted face up on Al metal substrate and forced towards the substrate with a press-jig, which leads to partial embedding of the chips into the substrate. More recent types of chip-first embedded actives have been developed by GE (see U.S. Pat. No. 5,353,498), Intel (see Ravi Mahajan et al., “Emerging Directions For Packaging Technologies”, Intel Technology Journal, Vol. 6, No. 2 (2002) pp. 62-75), Fraunhofer (see H. Reichl, et al., “The Third Dimension In Microelectronics Packaging”, 14th European Microelectronics and Packaging Conference & Exhibition Friedrichshafen, Germany, Jun. 23-25 (2003) pp. 1-6) and others since the early 1990s.
GE molds plastic around the chips and then builds up a multilayer interconnection over the top of the chips using polyimide films with vias formed using laser (see U.S. Pat. No. 5,353,498). Lockheed Martin also embedded chips and capacitors into a plastic-molded substrate similar to GE, except that they used some compliant materials around the chips to reduce thermal stress due to CTE (Coefficient of Thermal Expansion) mismatch between the chip and the molding materials (see U.S. Pat. No. 5,866,952).
Intel, Helsinki University and others are developing an embedded active technology that utilizes organic cores such as BT (Bismaleimide Triazine) laminate and FR4 instead of the plastic molded substrate of GE and Lockheed Martin. Intel followed up with a cavity-based approach with a microprocessor chip placed in the cavity in the BT core (see the Ravi Mahajan et al. paper). Helsinki university in collaboration with Imbera Electronics also uses a similar cavity-based approach to embed chips into FR4 core except that the build-up layers are processed on both surfaces of the core layer (see Helsinki Tarja Rapala-Virtanen, et al., “Embedding Passive and Active Components in PCB-Solution for Miniaturization”, The ECWC 10 Conference at IPC Printed Circuits Expo®, SMEMA Council APEX® and Designers Summit 05 (2005) pp. S16-1-1˜7). Another cavity-based approach developed by Virginia Polytech involves embedding their power MOSFET chips into the cavities of ceramic substrates (see Zhenxian Liang, et al., “Integrated Packaging of a 1 kW Switching Module Using a Novel Planar Integration Technology”, IEEE Transactions on Power Electronics, Vol. 19, No. 1 (2004) pp. 242-250).
Fraunhofer IZM and TU Berlin together have introduced the so-called Chip in Polymer (CIP) technology concept (see the H. Reichl, et al. paper). Chips are mounted on the substrate by die bonding followed by embedding inside a film of dielectric layer. Additionally, resistors can be also integrated into the package by deposition of very thin resistive metal films.
In SHIFT (Smart High-Integration Flex Technologies Flexible Laminate) project funded by EC (European Commission), eight research partners including IMEC, Technical University of Berlin, Fraunhofer IZM and others are developing a flexible embedded active structure without core (see http://www.vdivde-it.de/portale/shift/). Chips are placed face up on spin-coated flexible polyimide films and embedded into build-up layers by polyimide coating followed by metallization.
Casio Computer, in collaboration with CMK board manufacturer, is also developing chip-first embedded active technology by embedding wafer level packages (WLP) into boards (see http://world.casio.com/corporate/news/2006/ewlp.html).
Others disclosures relating to the chip-first approach include U.S. Pat. No. 6,396,148 and Yu-Hua Chen, et al., “Chip-in-Substrate Package, CiSP, Technology”, 2004 Electronics Packaging Technology Conference (2004) pp. 595-599.
In the chip-middle approach, embedded chips end up in the middle of build-up substrate, Shinko's approach being one of the representative examples of this approach (see Masahiro Sunohara, et al., “Development of Interconnect Technologies for Embedded Organic Packages”, 2003 Electronic Components and Technology Conference, New Orleans, May 27-30 (2003) pp. 1484-1489). A chip is placed face down onto a build-up layer like in an SMT (Surface Mount Technology) process and is fully embedded with subsequent build-up layers.
Another chip-middle active approach involves a laminated structure with active ICs. In this approach, multiple layers with active chips or passive components are fabricated separately and then laminated together. Matsushita is making the multiple layers by pressing conventional discrete passive components into a composite substrate made of ceramic powder and thermosetting resin with inner vias filled by conductive via paste, which is a mix of conductive filler, resin and a hardening agent (see Yoshiko Hara, “Matsushita embeds SoCs, components in substrate”, EE TIMES, September (2002)). Nokia uses a PWB (Printed Wiring Board) to make the laminated structures (see U.S. Pat. No. 6,974,724). Chips are placed inside the cavity of the PWB, similar to the chip-first embedded active approaches using organic core cavities. Their issue is that the electrically conductive layers on a PWB can provide electromagnetic shielding to RF chips embedded inside. Nokia has also secured a patent for this. SMIT is also trying to make a laminated structure of embedded active using LCP (liquid crystal polymer) core (see http://www.smitcenter.chalmers.se and http://smit.shu.edu.cn).
While current chip-first and chip-middle embedded active approaches can give many advantages such as small form factor and better electrical performance, they have also many other concerns. (1) serial chip-to-build-up processes accumulate yield losses associated with each process, leading to lower yield and higher cost. (2) defective chips cannot be easily reworked in current embedded package structure. This needs 100% known good die. (3) the interconnections in chip-first approach which are generally bumpless and very short metallurgical contacts can fatigue due to thermal stress. In addition, the electrical performance of chip-middle approach is compromised by long interconnections, like the flip-chip bumps. (4) Thermal management issues are also evident since the chip is totally embedded within less thermally conductive polymer materials of substrate or build-up layers.
However, the chip-last approach has not been explored to the extent of the chip-first and chip-middle approach. As an alternative to chip-first and chip-middle having many issues mentioned above, it would be desirable to explore a chip-last process for fabricating embedded active and/or discrete passive devices with improved processibility, electrical performance and thermal management capability.